T6L87 2002-06-24 1 toshiba cmos digital integrated circuit silicon monolithic T6L87 gate driver for tft lcd panels the T6L87 is a 256-channel output gate driver for tft lcd panels. this device accepts external input of the panel drive voltage, allowing you to change the low-level output voltage. thus, this device can be used for various tft lcd panel drive systems. features lcd drive output pins : 256 pins lcd drive voltage : max v ee + 40 v data transfer method : bidirectional shift register operating temperature : ? 20 to 75c package : tcp / cof features module for pc monitor please contact toshiba or a distributor f or the latest tcp specif ication and product line-up. tcp (tape carrier package) user area pitch in out T6L87 unit: m m
T6L87 2002-06-24 2 block diagram do/i g2 g3 g254 g255 g1 g256 u/d cpv control circuit unit output circuit unit 1 oe v off v gg v ee v ss v dd shift register input circuit unit di/o 2 oe 3 oe
T6L87 2002-06-24 3 pin assignment the above diagram shows the device?s pin configuration only and does not necessarily correspond to the pad layout on the chip. please contact toshiba or our distributors for the latest tcp / cof specification. g1 g2 g3 g254 g255 g256 268 267 266 15 14 13 v off v ee v ss di/o u/d cpv 1 oe 2 oe 3 oe do/i v dd v gg T6L87 (chip top view) 1 2 3 4 5 6 7 8 9 10 11 12
T6L87 2002-06-24 4 pin function pin name i/o function di/o do/i i/o vertical shift data i/o pins these pins are used to input and output shift data. these pins are switched between input and output by setting the u/d pin as shown below. u/d di/o do/i h input output l output input when set for input this pin is used to feed data into the shift registers at the first stage of the lcd driver. the data is latched into the shift registers at the rising edge of cpv. when set for output when two or more T6L87s are cascaded, this pin outputs the data to be fed into the next stage. this data changes state synchronously with the falling edge of cpv. u/d i transfer direction select pin this pin specifies the direction in which data is transferred through the shift registers. the shift register data is shifted synchronously with each rising edge of cpv as follows: when u/d is high, data is shifted in the direction u/d ?h?: g1 g2 g3 g4 g256 when u / d is low, the direction is reversed to give u/d ?l?: g256 g255 g254 g253 g1 the voltage applied to this pin must be a dc-level voltage that is either high (v dd ) or low (v ss ). cpv i vertical shift clock this is the shift clock for the shift registers. data is shifted through the shift registers synchronously with the rising edge of cpv. 1 oe to 3 oe i output enable pins these signals control the data appearing at the lcd panel drive pins (g1 through g256). oe doesn?t synchronize with the cpu. the v off voltage is output when oe 1 to oe 3 are high; normal shift data is output when oe 1 to oe 3 are low. g1 to g256 o lcd panel drive pins these pins output the shift register data or the voltage applied to v gg or v off depending on the control signals oe 1 to oe 3. v gg power supply for lcd drive v off analog reference voltage these pins accept as their input the off level at the lcd panel drive pins (g1 through g256). v ee power supply for lcd drive v dd power supply for the internal logic v ss power supply for the internal logic
T6L87 2002-06-24 5 device operation (see timing diagram) (1) shift data transfer method shift data u/d pin input output data transfer method h di/o do/i g1 g2 g3 g4 g256 l do/i di/o g256 g255 g254 g1 the input data (di/o or do/i) is latched into the internal register synchronously with the rising edge of the shift clock cpv. at the same time that the data is shifted to the next register at the next rise of cpv, new vertical shift data is latched into. in the output operation, the data in the last shift register (g256 or g 1 ) is output synchronously with the falling edge of cpv. (the output high voltage is the v dd level; the output low voltage is the v ss level.) (2) lcd panel drive outputs the lcd panel drive outputs are controlled by 1 oe to 3 oe as shown below. lcd panel drive outputs output enable pin lcd panel drive pins controller by oe output 1 oe ?h? g1, g4, g7, g250, g253, g256 2 oe ?h? g2, g5, g8, g251, g254 3 oe ?h? g3, g6, g9, g252, g255 v off 1 oe ?l? g1, g4, g7, g250, g253, g256 2 oe ?l? g2, g5, g8, g251, g254 3 oe ?l? g3, g6, g9, g252, g255 normal data output (3) voltage setting the v off level, which sets the lcd panel drive?s output low level, can take on any value between v ee to v ee 6 v. negative voltage output is also the same as the above. v gg v off 35 v v off v ee 0 to 6 v v gg v ss 1 0 to 25 v the logic input here means input pins di/o, do/i, cpv and 1 oe to 3 oe . make sure that the voltage applied to the u/d pin is a high ( v dd ) or low ( v ss ) dc-level voltage. v gg (20 v) (example) v dd (3.3 v) v ss (0 v) logic input logic output v ee v off ( 5 v) g1 to g256
T6L87 2002-06-24 6 timing diagram 1 up mode (u/d high) timing diagram 2 down mode (u/d low) di/o (input) cp v 1 oe 2 oe 3 oe g1 g2 g3 g4 g256 do/i (output) : this part is output which is controlled (fixed to v off ) by oe pin. 1 2 3 4 5 256 257 do/i (input) cp v 1 oe 2 oe 3 oe g256 g255 g254 g253 g1 di/o (output) : this part is output which is controlled (fixed to v off ) by oe pin. 1 2 3 4 5 256 257
T6L87 2002-06-24 7 absolute maximum ratings (v ss 0 v) parameter symbol rating unit supply voltage (1) v dd 0.3 to 6.0 supply voltage (2) v gg 0.3 to 42.0 supply voltage (3) v ee 20.0 to 0.3 supply voltage (4) v off v ee 0.3 ~v gg 0.3 supply voltage (5) v gg v ee 0.3 to 42.0 v input voltage v in 0.3 to v dd 0.3 v storage temperature t stg 55 to 125 c recommended operating conditions (v ss 0 v) parameter symbol rating unit supply voltage (1) v dd 2.7 to 3.6 supply voltage (2) v gg 10 to 35 supply voltage (3) v ee 15 to 5 supply voltage (4) v off v ee 0 to 6 supply voltage (5) v gg v ee 17 to 40 v operating temperature t opr 20 to 75 c operating frequency f cpv dc to 100 khz output load capacitance c l 300 (max) pf/pin electrical characteristics dc characteristics (v gg v ee 30 to 40 v, v dd 2.7 to 3.6 v, v ss 0 v, ta 20 to 75c) parameter symbol test circuit test condition min max unit relevant low level v il v ss 0.2 v dd input voltage high level v ih 0.8 v dd v dd v (note) low level v ol i ol 40 a v ss v ss 0.4 output voltage high level v oh i oh 40 a v dd 0.4 v dd v di/o, do/i low level r ol v out v ee 0.5 v output resistance high level r oh v out v gg 0.5 v 1000 g1 to g256 input leakage current i in 5 5 a (note) current consumption (1) i gg oe ?l?, non-load 20 v gg current consumption (2) i dd oe ?l? 15 v dd current consumption (3) i ee oe ?l? 10 a v ee note : these input pins include di/o, do/i, cpv, 1 oe to 3 oe
T6L87 2002-06-24 8 ac characteristics (v gg v ee 30 to 40 v, v dd 2.7 to 3.6 v, v ss 0 v, ta 20 to 75c) parameter symbol test circuit test condition min max unit clock frequency t cpv 100 khz cpv pulse width (h) t cpvh 4 s cpv pulse width (l) t cpvl 4 s data set-up time t sdi 200 ns data hold time t hdi 200 ns oe enable time t woe 1 s output delay time (1) t pddo c l 50 pf 800 output delay time (2) t pdg c l 300 pf 800 output delay time (3) t pdoe c l 300 pf 800 ns cpv t cpvh t cpvl t sdi t hdi di/o, do/i (input) v gg 50% 50% 50% 50% 50% 50% 50% g1 t pdg 50% t pdg 50% v off g2 to g256 t pdg 50% t pdg 50% v gg v off cpv do/i, di/o (output) v gg 50% 50% g256 t pddo 50% t pddo 50% v off 1 oe to 3 oe t woe v gg 50% 50% g1 to g256 v off t pdoe 50% t pdoe 50%
T6L87 2002-06-24 9 power supply sequence turn power on in the order v dd v ee v off input signal v gg turn power off in th reverse order. v dd v gg v ee , v off v ss
T6L87 2002-06-24 10 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. polyimide base film is hard and thin. be careful not to injure yourself on the film or to scratch any other parts with the film. try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. when cutting out the film, try to ensure that the film shavings do not cause accidents. after use, treat the leftover film and reel spacers as industrial waste. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebe restrictions on product use
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